1. Field of the Invention
The present invention relates generally to non-volatile memories in integrated circuit form which are programmable by the effect known as "hot carrier" effect and erasable by tunnel effect. More particularly, it relates to an improvement in a memory cell as well as to a memory of this type.
2. Description of Related Art
The first memories of the non-volatile type appeared under the name of EPROMs (electrically programmable read-only memories). In these memories, the memory cells comprise a floating-gate transistor that is programmable by so-called hot carrier effect. This programming consists of the application of a potential difference between the drain and the source of the transistor in the presence also of a high potential difference (of about 20 volts, this value varying according to the desired programming speed) between the control gate and the source. The application of the first of these potential differences generates an electrical field that gives rise to a flow of electrons in the channel. These electrons collide with atoms of the channel, causing the appearance of new free electrons. These electrons have very high energy (this is why the term "hot carriers" is used). The high difference in potential between the control gate and the source of the transistor gives rise to a strong electrical field between the floating gate and the substrate, the effect of which is that certain of these electrons are injected into the floating gate, thus putting the memory cell in a state known as a "programmed" state. The fact that the programming of a memory cell requires the application of voltages both to the control gate and to the drain of the floating-gate transistor eliminates the need for the use of a selection transistor to program one particular memory cell without programming the others. This results in a small surface area of silicon occupied by the memory array and therefore large-scale integration density. By contrast, the erasure of all the memory cells of the memory is done only in its totality by exposure to ultraviolet radiation. This is the essential drawback of these memories.
This is why EEPROMs (electrically erasable PROMS) made their appearance. These memories are electrically programmable and erasable by tunnel effect (Fowler Nordheim effect). The memory cells have a floating-gate transistor whose drain is connected to the bit line by means of a selection transistor. The gate of this transistor is connected to the word line. The gate of the floating-gate transistor is controlled by means of a bias transistor. The sources of the floating-gate transistors are common and generally connected to the ground. These transistors have an oxide layer between the substrate and the floating gate that is very thin (in the range of 2 to 3 nanometers) to enable the transfer of charges by tunnel effect (Fowler Nordheim effect). The advantage of EEPROMs as compared with EPROMs lies in the fact that each memory cell is programmable and erasable independently of the other memory cells. The tradeoff here is that a larger surface area of silicon is required and therefore a smaller scale of integration density.
A third type of memory has more recently made its appearance. This type comprises memories known as Flash EPROMs which combine the integration density of EPROMs with the ease of programming and erasure of EEPROMs. These memories can be programmed memory cell by memory cell using the hot carrier effect in the same way as the EPROMs. They are also erasable electrically by tunnel effect (Fowler Nordheim effect). The memory cells of a Flash EPROM memory comprise a floating-gate transistor that has an oxide layer whose thickness is greater (about 10 to 12 nm) than in the case of an EEPROM but smaller than in the case of an EPROM to enable erasure by tunnel effect. Indeed, for the erasure, a highly negative potential difference is created between the control gate and the source, the drain being left in the high impedance state or connected to the ground so that a high electrical field is created tending to remove the electrons from the floating gate.
If, in the memory array, the sources of the floating-gate transistors of each memory cell are common, it is impossible to erase just one memory cell alone. The memory can then be erased only in its totality, namely all the memory cells have to be erased at the same time. However, there are known ways of making Flash EPROM type memories that are electrically erasable by blocks of memory cells as shall be described with reference to FIG. 1. This figure shows an equivalent electrical diagram of the standard structure of a Flash EPROM type memory array. It is a partial view of a memory array organized in rows and columns, a word line (for example WL0 or WL1) being common to the memory cells of the same row (with an index 0 or 1 respectively) and a bit line (for example BL0, BL1, . . . , BL7) being common to the memory cells of the same column (with an index 0 to 7 respectively).
A floating-gate transistor forming the storage element of a memory cell is located at the intersection of each word line and each bit line. The floating-gate transistor of a memory cell located at the intersection of the row indexed i and the column indexed j of the memory array is designated in the figures by the reference TGFij. Thus, for example, FIG. 1 shows the floating-gate transistors TGF00 respectively at the intersection of the row 0 and the column 0, TGF07 at the intersection of the row 0 and the column 7, TGF10 at the intersection of the row 1 and the column 0 and TGF17 at the intersection of the row 1 and the column 7.
The control gates of the floating-gate transistors of the memory cells of a given row are connected to the corresponding word line. The drains of the floating-gate transistors of the memory cells of the same column, for example the column 0, are connected to the corresponding bit line, for example the line BL0. The sources of a block of memory cells of the same row are common and are connected to the drain of a selection transistor. For example, a block of this kind has eight adjacent memory cells that are adjacent along the axis of the rows so that a block corresponds to a word of one byte. Thus, the sources of eight adjacent floating-gate transistors TG00 to TG07 of the row 0 are connected to the drain of a selection transistor TS0. Similarly, the source of eight adjacent floating-gate transistors TGF10 to TGF17 of the row 1, which are adjacent along the axis of the columns to the transistors TGF00 to TGF07 respectively, are connected to the drain of a selection transistor TS1. The sources of the selection transistors of memory cell blocks that are adjacent along the axis of the columns (vertically in FIG. 1) are connected to the same selection line. Thus, in FIG. 1, the sources of the transistors TS0 and TS1 are connected to the selection line SL. The selection transistors are not floating-gate transistors. They are normally enhanced transistors. The selection lines of the memory array are designed to be taken to a potential that differs depending on whether the operation performed is a programming, erasure or read operation and enables the accurate biasing of the floating-gate transistors. To this end, the memory has means for obtaining individual access to each selection line such as an adapted decoder. Furthermore, the gates of the selection transistors of the blocks of memory cells of the same row receive the same control signal, for example the signal ssg0 for the row 0 and the signal ssg1 for the row 1. These signals are also applied to the corresponding word line, for example WL0 and WL1 respectively. In read mode, these signals dictate a potential ranging between the conduction threshold of a transistor in the "erased" state and that of a transistor in the "programmed" state for the selected memory cells (namely those of the selected row) and a zero potential (namely the ground potential) for the memory cells that are not selected (namely those of the other rows).
It will be noted that two floating-gate transistors that are adjacent along the axis of the columns share their drains. Similarly, the selection transistors of two blocks of adjacent memory cells along the axis of the columns share their sources. Thus, space is saved on the silicon substrate.
The standard structure illustrated here above of memories using Flash EPROM technology makes it possible to design a memory with an integration density close to that of the EPROM type memories while at the same time offering a function of erasure by tunnel effect for blocks of memory cells that is borrowed from the technology of EEPROMs. In particular, depending on the specifications of the product, the designer of the memory has the possibility of cutting off only a few blocks of memory cells. These blocks will then have the function of an EEPROM that is erasable independently of the other memory cells, the rest of the memory cells being erasable in their totality. This is very important in practice because the large-scale manufacture of an integrated circuit such as a memory cannot be done under economically acceptable conditions unless only one technology is used. Indeed, the choice of this technology determines firstly the method of manufacture and secondly the level of the voltages to be generated in the circuit (for example by means of load pumps or frequency multipliers) to carry out all the possible operations (programming, erasure or reading operations).
However, it is observed that if, during a read operation, two depleted transistors are in the same group (in the above-mentioned sense of the term) of cells that are not selected (and whose control gates therefore receive a zero voltage), then the two corresponding bit lines are short-circuited. This corrupts the result of the read operation. This is why the erasure operation must be carried out with a great deal of precaution so as to prevent the erased transistors from getting into a depleted state. In practice, the operation of erasure then comprises, for each floating-gate transistor, the following four steps which come after a preliminary operation to program the entire memory zone concerned by the erasure:
first, the application to the terminals of the transistor, during a specified temporal window, of the voltages needed to enable its erasure by tunnel effect; PA1 second, the testing of the erased state of the transistor, and a return to the first step if this is not the case; PA1 third, the testing of the depleted state of the transistor (testing of the negative sign of the conduction threshold); PA1 and fourth, if this is actually the case, the application to the terminals of the transistor, during a specific temporal window, of the required voltages to enable its reprogramming by hot carrier effect with a return to the third step for a fresh verification.
The operation of erasure is therefore delicate and lengthy in its implementation. This is why the memories using Flash EPROM technology have been further improved by the modification of the structure of the memory cells.
A memory cell thus modified is illustrated in FIG. 2, where the same elements as in FIG. 1 bear the same references. This structure is described in the article "A 128K Flash-EEPROM Using Double Polysilicon Technology" in the IEEE Journal of Solid State Circuits, Vol. SC-22, No. 5, October 1987. FIG. 2 shows only the four memory cells located at the intersection of the rows 0 and 1 on the one hand and the columns 0 and 1 on the other hand. Each floating-gate transistor TGFij has its source connected to the drain of a selection transistor TSij that is proper to it, the source of which is connected to a selection line SL common to all the memory cells of one column. Thus, the only difference with the structure of FIG. 1 lies in the fact that the source of each floating-gate transistor is connected to the selection line by means of a selection transistor that is proper to it instead of being common to the floating-gate transistors of the memory cells of the same group. This modified structure enables the floating-gate transistor of each memory cell to be insulated from the floating-gate transistors of the other memory cells. The result thereof is that the depleted or non-depleted state of the floating-gate transistor of the erased memory cells is not of vital importance. It is therefore no longer necessary to carry out the third and fourth steps stated here above during an operation of erasure, since whether the floating-gate transistor of the memory cells is in a depleted state or not is of no importance.